GIDL Suppression by Optimization of Junction Profiles in 22nm DGSOI nFETs
نویسنده
چکیده
It is shown by TCAD simulations how the gate-induced drain leakage which dominates the OFF-current in 22nm double-gate SOI nFETs with high-K gate stacks, can be minimized by proper variations of the junction profiles. Based on a microscopic, non-local model of band-to-band tunneling, transfer characteristics are computed after systematic changes in source/drain doping, body thickness, and HfO2 layer thickness. This is done under the constraint of a minimal degradation of the ON-current. The ITRS target for LSTP devices (10 pA/μm) can be met.
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تاریخ انتشار 2008